There is an ever-increasing interest in making electronic devices physically smaller. Consequently, electrical components become more compact as technologies are improved. However, such advances in technology also bring about additional problems. One such problem involves packaging components in devices.
Packaging is especially problematic with components incorporating multiple layers. One such component is the capacitor. Capacitors provide improved charge storage and energy density using multiple conductive layers and advanced dielectrics. As the layers become more complex and smaller in dimensions, problems arise with packaging. Housings for complex shapes defining contoured layer stacks are needed.
Thus, there is a need in the art for housing designs which are adapted to new capacitor stack shapes, and which improve packaging efficiency without sacrificing substantial performance of the component.